1. Field of the Invention
The present invention relates to a transfer material for transferring a fine wiring pattern or circuit components to a substrate, and a method for producing the same. Furthermore, the present invention relates to a wiring substrate on which a wiring pattern or a circuit component is formed and a method for producing the same.
2. Related Background Art
Recently, with a demand for high performance and miniaturization of electronic equipment, high-density and high-performance semiconductor devices increasingly have been desired. This leads to a demand for a small size and high density circuit substrate on which such semiconductor devices are to be mounted.
In order to meet such demands, a connection method using inner via holes (IVHs) that can connect between wiring patterns of large-scale integrated circuits (LSIs) or circuit components in the shortest distance has been developed in various fields. In general, an example of wiring patterns having such IVH configurations includes a multi-layered ceramic wiring substrate, a multi-layered wiring substrate produced by a build-up method, a multi-layered composite wiring substrate including a mixture of a resin and an inorganic filler, and the like.
The multi-layered ceramic wiring substrate can be produced, for example, by a following method. First, a plurality of green sheets including a ceramic powder such as alumina, etc., an organic binder and a plasticizer are prepared. Then, each of the green sheets is provided with via holes and the via holes are filled with a conductive paste. Thereafter, a wiring pattern is printed on the green sheets, and the printed green sheets are laminated. Then, the thus obtained laminate is subjected to a binder removing treatment and a firing treatment, thus forming a multi-layered ceramic wiring substrate. Since the thus obtained multi-layered ceramic wiring substrate has an IVH structure, an extremely high-density wiring pattern can be formed. Therefore, such multi-layered ceramic wiring substrates are suitable for miniaturization of electronic equipment.
Also, the print wiring substrate produced by the build-up method, which imitates the structure of the multi-layered ceramic wiring substrate, has been developed in various fields. For example, JP9 (1997)-116267A, JP9 (1997)-51168A, etc. disclose a conventional general build-up method. In this method, a conventionally used glass-epoxy substrate is used as a core and a photosensitive insulating layer is formed on the surface of the substrate. The surface is provided with via holes by photolithography, the entire surface is copper-plated, and then the copper-plated surface is subjected to a chemical etching process, to thus form a wiring pattern.
Furthermore, JP9 (1997)-326562A discloses a method in which a conductive paste is filled in via holes processed by photolithography as in the build-up method. JP9 (1997)-36551A, JP10 (1998)-51139A, etc. disclose a method for producing a multi-layered substrate by forming a conductive circuit on one surface of a hard insulating base material and an adhesive layer on another, respectively; providing through holes thereon; filling the through holes with a conductive paste; and then laminating a plurality of base materials to thus form a multi-layered substrate.
Furthermore, specification of Japanese Patent Nos. 2601128, 2603053, 2587596 disclose a method for producing a multi-layered structure in which an aramid-epoxy prepreg is provided with through holes by laser machining, the through holes are filled with a conductive paste, and then a copper foil is laminated and patterning is carried out. This substrate is used as a core, and is impregnated by prepregs with a conductive paste, to thus form a multi-layer structure.
As mentioned above, similar to the above-mentioned multi-layer ceramic wiring pattern, the connection method using IVHs for, for example, a resin based printing wiring substrate, allows an electrical connection only between the layers necessary to be connected. Furthermore, since no through holes are provided on the top layer of the substrate, the mountability is also excellent.
However, in general, such a high-density mounted resin based printing wiring substrate including an IVH structure has a low thermal conductivity. As the mounting density of components becomes higher, it is getting more difficult to release heat that has been generated in the components.
In addition, in the year 2000, a clock frequency of a CPU is about 1 GHz. It is estimated that with the sophistication in the function of the CPU, its electric power consumption accordingly reaches 100 to 150 W per chip.
In general, a ceramic wiring substrate excellent in the thermal conductivity has an excellent heat releasing property, but there are some disadvantages, for example, it is relatively expensive, it is poor in impact resistance property when it is applicable for a substrate or a module used for portable terminals, and the like.
Therefore, in order to solve the problem of the thermal conductivity of the resin based printing wiring substrate, or in order to form a capacitor on the resin multi-layered substrate, a structure in which a resin based wiring substrate and a ceramic substrate are laminated is proposed in specification of Japanese Patent No. 3063427 or JP7 (1995)-142867.
Furthermore, a multi-layered composite wiring substrate for enhancing the thermal conductivity of a base material itself is disclosed in JP9 (1997)-270584A, JP8 (1996)-125291A, JP8 (1996)-288596A, JP10 (1998)-173097A, etc. This multi-layered composite substrate is formed by mixing a thermosetting resin such as an epoxy resin and an inorganic filler having an excellent thermal conductivity (for example, a ceramic powder, etc.) to make a composite. This substrate can contain an inorganic filler with high density, so that the thermal conductivity can be enhanced. Furthermore, by selecting a suitable inorganic filler, for example, the dielectric constant, the coefficient of thermal expansion, or the like, can be controlled suitably.
On the other hand, in developing the high density mounting of the substrate, the formation of a fine wiring pattern is important. A generally used method for forming the wiring pattern in the multi-layered ceramic wiring substrate includes, for example, a screen printing of a thick film conductive paste onto the ceramic substrate followed by firing for hardening. However, in this screen printing method, it is said that the mass production of wiring patterns having a line width of 100 μm or less is difficult.
Furthermore, in a usual printing wiring substrate, for example, a wiring pattern is formed by a subtractive method. In this subtractive method, the wiring pattern is formed by chemically etching a copper foil having a thickness of about 18 to 35 μm. Also in this case, it is said that the mass production of the wiring patterns having a line width of 75 μm or less is difficult. In order to make the wiring pattern finer, the copper foil is required to be thin.
Furthermore, in the subtractive method, since the wiring pattern is projected to the surface of the substrate, it is difficult to mount a solder or conductive adhesives, etc. for an electric connection on the bump formed on a semiconductor device. Furthermore, the bump moves to a place between the wiring patterns, which may lead to a short circuit. Furthermore, the projected wiring patterns may damage the sealing with a sealing resin in a later process.
In addition, in the printing wiring pattern by the build-up method, besides the subtractive method, an additive method tends to be employed. By the additive method, wiring patterns are plated selectively on the surface of a substrate on which resist is formed. This allows the formation of wiring patterns having a line width of about 30 μm. However, the additive method has a problem in that the adhesive strength of the wiring patterns to the substrate is lower as compared with the subtractive method.
A method is proposed in which fine wiring patterns that have been formed beforehand are subjected to a pattern test, and only excellent wiring patterns are transferred to the desired substrate. For example, U.S. Pat. No. 5,407,511 discloses a method in which a fine wiring pattern that has been formed beforehand on the surface of a carbon plate is formed by printing or firing, and then transferred to a ceramic substrate. Furthermore, JP10(1998)-84186A, and JP10(1998)-41611 disclose a method of transferring a copper foil wiring pattern that has been formed on a mold release support plate to a prepreg. Similarly, JP11(1999)-261219A discloses a method of transferring a copper foil wiring pattern to the mold release support plate formed of a copper foil via a peel layer made of nickel-phosphorus alloy. Furthermore, JP8(1996)-330709A discloses a method of transferring a copper foil wiring pattern to a substrate by utilizing a difference in adhesive degree between a roughened surface and a bright surface.
In the wiring patterns transferred by such transferring methods, a wiring pattern is embedded in the surface of the substrate, so that the substrate surface becomes flat and can avoid the problem due to the projection of the wiring pattern. Furthermore, JP10(1998)-190191A discloses an effect of compressing a conductive via paste to be filled in through holes by an amount of the thickness of the wiring pattern when the wiring pattern is embedded in the surface of the substrate.
In recent years, a further fining of the wiring pattern is demanded. However, it is difficult to form a finer wiring pattern on the mold release support plate by conventional techniques for transferring the wiring pattern. Namely, for example, when a copper foil adhered to the mold release support plate is formed into a pattern, if the adhesive strength of the copper foil with respect to the mold release support plate is weak, the fine wiring pattern is peeled off in a chemical etching process. On the contrary, in a case where the adhesive strength is strong, after the transfer of the wiring pattern to the substrate, when the mold release support plate is peeled off, the wiring pattern is peeled off together. Furthermore, there is also a method in which the surface of the copper foil is roughened so as to make the adhesive strength between the copper foil and the substrate stronger than the adhesive strength between the copper foil and the release molding support plate, thereby transferring the copper foil onto the substrate. However, with this method, it is difficult to form a fine wiring pattern.
Furthermore, in sintering the conductive paste containing a conductive powder, unlike a metal layer such as a copper foil, the electric conductivity is poor, which may lead to a problem about a trend toward a high frequency in the future.
On the contrary, conventionally, it was difficult to form a ceramic multi-layered substrate in which a wiring pattern is formed of a metal foil such as a copper foil, etc. because the formation of a wiring pattern by the use of a metal foil on a green sheet without damaging the property of the green sheet is difficult.
Furthermore, in a production method of the resin based printing wiring pattern, conventionally, a general method is to laminate layers sequentially. A plurality of press processes are needed. Therefore, in order to realize an accurate interlayer connection, complicated steps for correcting hardening and shrinkage occurring in each press process cannot be avoided.
Furthermore, for the purpose of solving the problem of the thermal conductivity of the resin printing wiring substrate, or for forming a capacitor with a capacitance on the resin multi-layered substrate, a laminated structure itself of a resin printing wiring substrate and a ceramic substrate has been proposed. However, in fact, since damages such as cracks are generated mainly in the ceramic layer through the laminating process etc., it was difficult to realize this structure.